This invention relates to the field of binary digital decoders and more particularly to the acquisition of data sampling synchronization and power-up timing using signals present in an asynchronous decoder.
Asychronous digital detectors requiring no bit or frame synchronization in order to detect a predetermined code address have been disclosed in U.S. Pat. Nos. 3,801,956 and 3,855,576, both being assigned to the same assignee as is the present invention. The first of the above-referenced patents discloses a system for asynchronously detecting one code word by cycling the sampled bits of the received data in parallel with the bits of the stored code address word, and counting correlations. The second referenced patent discloses a system using the asynchronous first word detect to provide synchronization for the second word detect. Thus, a relatively long preamble or framing data transmission is unnecessary and a large number of code addresses are made available.
Data terminals are now being used which must detect a binary digital address in a train of binary signals then, upon such detection, accurately decode the subsequent data message. With such terminals, it is possible to provide synchronization by transmitting a lengthy preamble during which a VCO is locked up and kept locked during the transmission by a phase locked loop. While operationally satisfactory, this requires much additional circuitry in the decoder. It is also possible to achieve synchronization with the decoder of the last referenced patent by using only second code words having a high number of level transmissions, thus reducing the detect time ambiguity caused by multiple detects of a word having a low number of transmissions. However, this reduces the number of possible code addresses and makes it necessary to individually select the second word of each assigned code address.